We are looking for a qualified Senior Verification engineer who wants to lead an effort to add verification capabilities using UVM and SystemVerilog to the group. This person will formulate guidelines to develop verification test bench infrastructure using UVM. Initially, it will be an individual contributory role and will likely lead into a lot more, depending upon the capabilities of the person.
This is a great opportunity for someone with a verification centric mindset and at least 3-4 years of UVM and 4-5 years of SystemVerilog experience. The ideal candidate should have an overall experience of at least 10 plus years.
The requirements for this position are:
10+ years verification experience
Expertise in HVL and HDL(SystemVerilog, Verilog)
Advanced knowledge of HVL methodology (UVM/OVM/VMM)
Solid verification skills in problem solving, constrained random testing, and debugging.
Knowledge of industry standard interfaces.
Experience writing scripts in languages such as Perl or Python a plus.
Programming experience in C/C++/assembly a plus.
Experience defining coverage space and writing coverage model a plus.
Experience with SystemVerilog Assertion (SVA) a plus.
Should be a team player with excellent communication skills and the desire to take on diverse challenges.
This position is located about 50 miles from New York City, in Long Island, NY. Relocation assistance will be provided, if needed.