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4 days ago
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Design Engineer - Design Verification / Wireless Technology / Hardware


Salary band: $10k - $15k
Location: North America, United States, California
Job type: Permanent
Contact: Randstad Engineering
Category: Design Engineer
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Job Description:

A company focused on inventing mobile technology breakthroughs is looking for a Verification Engineer in the Santa Clara, CA area. This is a 4-month CONTRACT position. No per diem available. Responsibilities for the Design Engineer * Candidate with be responsible for design verification methodology implementation for C/C++ models for functional coverage * Candidate will drive the implementation of functional coverage methodology including adding cover points to C/C++ models, debugging flow issues, collecting coverage, analyzing coverage reports, identifying holes in coverage, working with system model designers to generate test vectors for improving coverage, and presenting detailed results/recommendations to the team * Candidate will work primarily with System engineers, RTL design engineers and RTL Design Verification engineers across multiple sites to achieve functional coverage closure for C/C++ models Requirements for the Design Engineer * Experience with High-Level Synthesis tools & SystemC * Bachelor of Science in Electrical Engineering Preferred: Master's or equivalent experience * Working knowledge of version control systems (GIT, ClearCase preferred) Benefits * Healthcare * 401K Related Words: version control systems, electrical engineering, verification methodology implementation ,design verification,engineer,design engineer
Job Description:

A company focused on inventing mobile technology breakthroughs is looking for a Verification Engineer in the Santa Clara, CA area. This is a 4-month CONTRACT position. No per diem available. Responsibilities for the Design Engineer * Candidate with be responsible for design verification methodology implementation for C/C++ models for functional coverage * Candidate will drive the implementation of functional coverage methodology including adding cover points to C/C++ models, debugging flow issues, collecting coverage, analyzing coverage reports, identifying holes in coverage, working with system model designers to generate test vectors for improving coverage, and presenting detailed results/recommendations to the team * Candidate will work primarily with System engineers, RTL design engineers and RTL Design Verification engineers across multiple sites to achieve functional coverage closure for C/C++ models Requirements for the Design Engineer * Experience with High-Level Synthesis tools & SystemC * Bachelor of Science in Electrical Engineering Preferred: Master's or equivalent experience * Working knowledge of version control systems (GIT, ClearCase preferred) Benefits * Healthcare * 401K Related Words: version control systems, electrical engineering, verification methodology implementation ,design verification,engineer,design engineer

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